| Name | Version | Summary | date |
|---|---|---|---|
| lctime | 0.0.24 | CMOS standard-cell characterization kit. | 2024-04-15 19:48:00 |
| librecell | 0.0.23 | DEPRECATED - use `lctime` and `lclayout` packages - CMOS layout generator and characterization. | 2024-04-14 20:31:06 |
| librecell-layout | 0.0.23 | DEPRECATED - use `lclayout` package instead - CMOS standard-cell layout generator. | 2024-04-14 20:28:43 |
| librecell-lib | 0.0.23 | DEPRECATED - use `lctime` - CMOS standard-cell characterization kit. | 2024-04-14 20:28:09 |
| hdl-registers | 5.1.3 | An open-source HDL register interface code generator fast enough to run in real time | 2024-04-03 07:05:30 |
| peakrdl-regblock | 0.22.0 | Compile SystemRDL into a SystemVerilog control/status register (CSR) block | 2024-04-01 05:27:07 |
| hour | day | week | total |
|---|---|---|---|
| 40 | 1248 | 9462 | 204047 |